Ferroelectric random access memories (FRAMs) are a type of nonvolatile memory devices that use remnant polarization that remains after a voltage potential is applied to a ferroelectric material and then removed. FRAM devices are nonvolatile in that stored information remains after power is turned off, and may be high speed, large capacity and low power. FRAM devices can include a thin film ferroelectric material of Pb(ZrxTi1-x)O3 (‘PZT’), SrBi2Ta2O9 (‘SBT’), SrxBi2-y(TaiNbj)2O9-z (‘SBTN’), Bi4-xLaxTi3O12 (‘BLT).
Because ferroelectric materials are crystalline, it may be important to provide a lower electrode material beneath the ferroelectric material. The lower electrode material can be platinum (Pt), iridium (Ir), ruthenium (Ru) or the like, or can be a hybrid electrode ruthenium oxide (RuOx) that is stacked on the aforementioned materials. A hybrid electrode can include an oxide film that may inhibit or improve a fatigue phenomenon in which a remnant polarization (Pr) value decreases over time as an electric pulse is applied and switched. The fatigue phenomenon may be due to an oxygen depletion defect that can occur in a boundary between a ferroelectric and an electrode material. Providing an oxidation film between the ferroelectric and the electrode material may reduce oxygen depletion at the interface so that the fatigue phenomenon is inhibited or improved.
A semiconductor device including a ferroelectric planar capacitor with an oxide electrode is shown in FIG. 1A. Referring to FIG. 1A, a device isolation region (field oxide) 4 for defining active region is formed on a substrate 2. A gate electrode 8 is formed on the substrate 2 having the device isolation region 4. A gate insulating film 6 is interposed between the gate electrode 8 and the substrate 2. A gate spacer 12 is formed on sidewalls of the gate electrode 8. Source and drain regions 16 each consisting of a lightly doped region 10 and a heavily doped region 14 are formed in the substrate 2 adjacent to the gate electrode 8. On the substrate including the gate electrode 8 is formed a first interlayer insulating layer 18. A bit line 22 is formed such that it penetrates the first interlayer insulating layer 18 and electrically contacts with the drain region 16. A second interlayer insulating layer 24 is formed on the bit line 22 and the first interlayer insulating layer 18. A contact plug 30 is formed such that it penetrates an interlayer insulating layer 26 including the second interlayer insulating layer 24 and the first interlayer insulating layer 18 and electrically contacts with the source region 16. On the interlayer insulating layer 26 including the contact plug 30 is formed a planar type lower electrode 36 consisting of a metal film 32 electrically connected with the contact plug 30 and a metal oxide film 34. A ferroelectric film 40 and upper electrode 42 are stacked on the lower electrode 36.
Although the hybrid lower electrode may reduce the occurrence of polarization fatigue, the stacked metal film and the metal oxide film may be difficult to fabricate as thin films and the fabrication process may be more complicated. Additionally, the ferroelectric film 40 may be degenerated during a subsequent etch process for forming a planar capacitor. It may also be difficult to manufacture the three-dimensional structure capacitors as shown in FIGS. 1B and 1C using a stacked hybrid electrode.
Referring to FIG. 1B, a stack type hybrid lower electrode 37 is shown in which a metal film 33 and a metal oxide film 35 are stacked and then patterned. A ferroelectric film 41 is deposited on the lower electrode 37.
As shown in FIG. 1C, the metal film 33 and the metal oxide film 35 are respectively patterned to form the hybrid lower electrode 37. The ferroelectric film 41 is formed on the hybrid lower electrode 37. Alignment margins during the associated photolithography process may become difficult to achieve as integration density is increased, and the fabrication process may become more difficult.